公开(公告)号：US20230169032A1

公开(公告)日：2023-06-01

申请号：US18102568

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F15/7889 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/3869 ,  G06F9/5038 ,  G06F15/17312

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20200334196A1

公开(公告)日：2020-10-22

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.