公开(公告)号：US20230169032A1

公开(公告)日：2023-06-01

申请号：US18102568

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F15/7889 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/3869 ,  G06F9/5038 ,  G06F15/17312

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20200334196A1

公开(公告)日：2020-10-22

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20160299849A1

公开(公告)日：2016-10-13

申请号：US14680287

申请日：2015-04-07

Applicant: Intel Corporation

Inventor： ANDREW J. HERDRICH ,  EDWIN VERPLANKE ,  RAVISHANKAR IYER ,  CHRISTOPHER C. GIANOS ,  JEFFREY D. CHAMBERLAIN ,  RONAK SINGHAL ,  JULIUS MANDELBLAT ,  BRET L. TOLL

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/604

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Abstract translation: 具有代码和数据优先级的缓存分配的系统和方法。 示例系统可以包括：高速缓存; 处理核心，可操作地耦合到高速缓存; 以及高速缓存控制逻辑，响应于接收到包括请求类型的标识符和服务等级的标识符的高速缓存填充请求，以识别对应于与请求类型和类别相关联的容量位掩码的高速缓存的子集 的服务。