公开(公告)号：US20180097630A1

公开(公告)日：2018-04-05

申请号：US15283315

申请日：2016-10-01

Applicant: INTEL CORPORATION

Inventor： VIKRAM SURESH ,  SUDHIR SATPATHY ,  SANU MATHEW

IPC: H04L9/32 ,  H04L9/06 ,  G06F7/72 ,  G06F17/16

CPC classification number: H04L9/3236 ,  G06F7/724 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/12 ,  H04L2209/24

Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.

公开(公告)号：US20220085993A1

公开(公告)日：2022-03-17

申请号：US17019864

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： RAGHAVAN KUMAR ,  SUDHIR SATPATHY ,  VIKRAM SURESH ,  SANU MATHEW

IPC: H04L9/08 ,  H04L9/32 ,  H04L9/30

Abstract: An apparatus includes a processor to generate a random exponent having a fixed bit width, divide the random exponent into a pre-exponent portion and a post-exponent portion at a random bit position in the fixed bit width, and generate a cryptographic key using the pre-exponent portion and the post exponent portion