公开(公告)号：US20220415736A1

公开(公告)日：2022-12-29

申请号：US17356036

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Shashi VYAS ,  Andy Chih-Hung WEI ,  Charles H. WALLACE ,  Sachin PANDIJA

IPC: H01L23/29 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L23/31 ,  H01L21/56 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.