公开(公告)号：US20220415736A1

公开(公告)日：2022-12-29

申请号：US17356036

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Shashi VYAS ,  Andy Chih-Hung WEI ,  Charles H. WALLACE ,  Sachin PANDIJA

IPC: H01L23/29 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L23/31 ,  H01L21/56 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to protecting metal gates within transistor gate structures during SAC patterning. In particular, embodiments include area selective deposition techniques to deposit films on the gate or on a gate cap that have a good selectivity to SAC etch. In embodiments the film may include a combination of zirconium and/or oxygen, or may include zirconium oxide. Other embodiments may be described and/or claimed.

公开(公告)号：US20230178426A1

公开(公告)日：2023-06-08

申请号：US17541976

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Tiffany ZINK ,  Shashi VYAS ,  Weimin HAN ,  Sudipto NASKAR ,  Charles H. WALLACE

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/5226 ,  H01L21/76877 ,  H01L23/53228

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

公开(公告)号：US20220416057A1

公开(公告)日：2022-12-29

申请号：US17358559

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Shashi VYAS ,  Andy Chih-Hung WEI ,  Leonard P. GULER

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L21/28 ,  H01L21/8234

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to manufacturing a gate structure that includes adjacent gates that are coupled with the first fin and a second fin, with a metal gate cut across the adjacent gates and a trench connector between the adjacent gates that electrically couples the first fin and the second fin. Other embodiments may be described and/or claimed.