公开(公告)号：US20240095206A1

公开(公告)日：2024-03-21

申请号：US18525289

申请日：2023-11-30

Applicant: Intel Corporation

Inventor： Sampath Dakshinamurthy ,  Pooja Jadhav ,  Neethumol O.U. ,  Lakshmipriya Seshan

IPC: G06F13/42

CPC classification number: G06F13/4273 ,  G06F2213/0064

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to semiconductor interconnects, such as on-package die-to-die (D2D) interconnects, for example. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.