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    Approximate data bus inversion technique for latency sensitive applications
    1.
    发明授权
    Approximate data bus inversion technique for latency sensitive applications 有权

    公开(公告)号：US12117960B2

    公开(公告)日：2024-10-15

    申请号：US17029288

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4291 ,  G06F13/4068 ,  G06F13/423

    Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

    Link layer-PHY interface adapter
    2.
    发明授权
    Link layer-PHY interface adapter 有权

    公开(公告)号：US11971841B2

    公开(公告)日：2024-04-30

    申请号：US17008542

    申请日：2020-08-31

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Swadesh Choudhary ,  Mahesh Wagh ,  Lakshmipriya Seshan

    IPC: G06F13/42 ,  G06F13/28

    CPC classification number: G06F13/4286 ,  G06F13/287 ,  G06F13/4226

    Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

    DIE-TO-DIE INTERCONNECT
    3.
    发明申请
    DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220342840A1

    公开(公告)日：2022-10-27

    申请号：US17852865

    申请日：2022-06-29

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

    IPC: G06F13/42

    Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

    Scalable and interoperable PHYLESS die-to-die IO solution
    4.
    发明授权
    Scalable and interoperable PHYLESS die-to-die IO solution 有权

    公开(公告)号：US12159840B2

    公开(公告)日：2024-12-03

    申请号：US16910023

    申请日：2020-06-23

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Juan Zeng ,  Peipei Wang ,  Ahmad Siddiqui ,  Lakshmipriya Seshan

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/538

    Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

    DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
    5.
    发明申请
    DIE-TO-DIE INTERCONNECT PROTOCOL LAYER 有权

    公开(公告)号：US20220327084A1

    公开(公告)日：2022-10-13

    申请号：US17853502

    申请日：2022-06-29

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

    IPC: G06F13/42 ,  G06F13/40 ,  G06F11/10

    Abstract: Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.

    LINK LAYER-PHY INTERFACE ADAPTER
    7.
    发明申请
    LINK LAYER-PHY INTERFACE ADAPTER 有权

    公开(公告)号：US20250013600A1

    公开(公告)日：2025-01-09

    申请号：US18648122

    申请日：2024-04-26

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Swadesh Choudhary ,  Mahesh Wagh ,  Lakshmipriya Seshan

    IPC: G06F13/42 ,  G06F13/28

    Abstract: An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
    9.
    发明申请
    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS 有权

    公开(公告)号：US20220327083A1

    公开(公告)日：2022-10-13

    申请号：US17844366

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

    IPC: G06F13/42 ,  H01L23/538 ,  G06F13/40

    Abstract: In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.

    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES
    10.
    发明申请
    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES 有权

    公开(公告)号：US20210344354A1

    公开(公告)日：2021-11-04

    申请号：US17359517

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald S. Pasdast

    IPC: H03M13/11 ,  H03M13/00

    Abstract: In one embodiment, an apparatus includes PHY circuitry to implement a PHY-based retry technique, e.g., in die-to-die interfaces. The PHY circuitry includes a retry buffer to buffer data provided by the interface controller and error detection code generation circuitry to generate error detection codes based on input data. The PHY circuitry is to implement the retry technique by detecting a stall signal asserted by another apparatus across the channel, causing the error detection code generation circuitry to generate error detection codes based on data in the retry buffer, and transmitting the data from the retry buffer and its corresponding error detection codes across the channel to the other apparatus.

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