公开(公告)号：US11604730B2

公开(公告)日：2023-03-14

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/08 ,  G06F12/0815 ,  G06F11/10 ,  G06F12/0893

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

公开(公告)号：US20210200678A1

公开(公告)日：2021-07-01

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/0815 ,  G06F12/0893 ,  G06F11/10

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.