公开(公告)号：US08977811B2

公开(公告)日：2015-03-10

申请号：US13914993

申请日：2013-06-11

Applicant: Intel Corporation

Inventor： Philip Abraham ,  Stanley S. Kulick ,  Randy B. Osborne

IPC: G06F12/00 ,  G06F9/38 ,  G06F12/08 ,  G06F9/52 ,  G06F11/14 ,  G06F13/16

CPC classification number: G06F12/00 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/528 ,  G06F11/141 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/1626

Abstract: Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了用于提高存储器件的产量和效率的方法和装置。 在一个实施例中，存储器控制器可以包括调度器逻辑，以最佳方式向存储器件发出读或写请求，例如最大化带宽和/或减少等待时间。 还公开并要求保护其他实施例。

公开(公告)号：US20240330053A1

公开(公告)日：2024-10-03

申请号：US18194408

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Philip Abraham ,  Priya Autee ,  Stephen Van Doren ,  Yen-Cheng Liu ,  Rajesh Sankaran ,  Kameswar Subramaniam ,  Ritesh Parikh

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5016 ,  G06F9/3009 ,  G06F9/5044

Abstract: Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.

公开(公告)号：US20210200678A1

公开(公告)日：2021-07-01

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/0815 ,  G06F12/0893 ,  G06F11/10

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

公开(公告)号：US20190114243A1

公开(公告)日：2019-04-18

申请号：US16218078

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Umberto Santoni ,  Rahul Pal ,  Philip Abraham ,  Mahesh Mamidipaka ,  C. Santhosh

IPC: G06F11/273 ,  G06F11/16

CPC classification number: G06F11/273 ,  G06F11/1004 ,  G06F11/1616 ,  G06F11/1629 ,  G06F11/1633 ,  G06F11/1641 ,  G06F11/1666

Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

公开(公告)号：US20230315632A1

公开(公告)日：2023-10-05

申请号：US17711471

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Philip Abraham ,  Stephen Van Doren ,  Ritu Gupta ,  Andrew Herdrich

IPC: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

CPC classification number: G06F12/0811 ,  G06F12/0846 ,  G06F12/084

Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

公开(公告)号：US11604730B2

公开(公告)日：2023-03-14

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/08 ,  G06F12/0815 ,  G06F11/10 ,  G06F12/0893

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

公开(公告)号：US10831628B2

公开(公告)日：2020-11-10

申请号：US16218078

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Umberto Santoni ,  Rahul Pal ,  Philip Abraham ,  Mahesh Mamidipaka ,  C Santhosh

IPC: G06F11/273 ,  G06F11/16 ,  G06F11/10

Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.