公开(公告)号：US11514550B2

公开(公告)日：2022-11-29

申请号：US16916670

申请日：2020-06-30

Applicant: INTEL CORPORATION

Inventor： Yunbiao Lin ,  Changliang Wang ,  Satyanantha Ramagopal Musunuri ,  David Puffer ,  David J. Cowperthwaite ,  Bryan R. White ,  Balaji Vembu

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/14 ,  G06F9/451 ,  G09G5/00 ,  G09G5/36 ,  G06F12/10 ,  G06F12/1009

Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.

公开(公告)号：US10706493B2

公开(公告)日：2020-07-07

申请号：US15858583

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Yunbiao Lin ,  Changliang Wang ,  Satyanantha Ramagopal Musunuri ,  David Puffer ,  David J. Cowperthwaite ,  Bryan R White ,  Balaji Vembu

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/14 ,  G06F9/451 ,  G09G5/00 ,  G09G5/36

Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.