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公开(公告)号：US10776156B2
公开(公告)日：2020-09-15
申请号：US15281260
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Altug Koker , Prasoonkumar Surti , Guei-Yuan Lueh , Subramaniam Maiyuran , Tomas G. Akenine-Moller , David J. Cowperthwaite , Balaji Vembu
Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a thread dispatcher to assign a priority class to each of a plurality of processing threads prior to dispatching the one or more processing threads, a plurality of execution units to process the threads, a shared resource coupled to each of the plurality of execution units and an arbitration unit to grant access to the shared resource to a first of the plurality of execution units based on the priority class of a thread being executed at the first execution unit.
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公开(公告)号：US20180300845A1
公开(公告)日：2018-10-18
申请号：US15488547
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Adam T. Lake , Guei-Yuan Lueh , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Abhishek R. Appu , Altug Koker , Subramaniam M. Maiyuran , Eric C. Samson , David J. Cowperthwaite , Zhi Wang , Kun Tian , David Puffer , Brian T. Lewis
Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
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公开(公告)号：US11715174B2
公开(公告)日：2023-08-01
申请号：US17685445
申请日：2022-03-03
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
CPC classification number: G06T1/20 , G06F9/3887 , G06F9/4806 , G06F9/4843 , G06F9/4881 , G06F9/5083 , G06F9/5088 , G06F11/0793 , G06F2209/5017 , G06T2200/28 , G06T2210/52 , Y02D10/00
Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.
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公开(公告)号：US11270406B2
公开(公告)日：2022-03-08
申请号：US17099118
申请日：2020-11-16
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.
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公开(公告)号：US11232536B2
公开(公告)日：2022-01-25
申请号：US16791514
申请日：2020-02-14
Applicant: Intel Corporation
Inventor： Adam T. Lake , Guei-Yuan Lueh , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Abhishek R. Appu , Altug Koker , Subramaniam M. Maiyuran , Eric C. Samson , David J. Cowperthwaite , Zhi Wang , Kun Tian , David Puffer , Brian T. Lewis
IPC: G06T1/60 , G06T1/20 , G06F8/41 , G06F12/0862
Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
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Patent Agency Ranking
公开(公告)号：US20200258191A1
公开(公告)日：2020-08-13
申请号：US16791514
申请日：2020-02-14
Applicant: Intel Corporation
Inventor： Adam T. Lake , Guei-Yuan Lueh , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Abhishek R. Appu , Altug Koker , Subramaniam M. Maiyuran , Eric C. Samson , David J. Cowperthwaite , Zhi Wang , Kun Tian , David Puffer , Brian T. Lewis
Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
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公开(公告)号：US10706493B2
公开(公告)日：2020-07-07
申请号：US15858583
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Yunbiao Lin , Changliang Wang , Satyanantha Ramagopal Musunuri , David Puffer , David J. Cowperthwaite , Bryan R White , Balaji Vembu
Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.
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公开(公告)号：US10460417B2
公开(公告)日：2019-10-29
申请号：US16010692
申请日：2018-06-18
Applicant: Intel Corporation
Inventor： Murali Ramadoss , Balaji Vembu , Eric C. Samson , Kun Tian , David J. Cowperthwaite , Altug Koker , Zhi Wang , Joydeep Ray , Subramaniam M. Maiyuran , Abhishek R. Appu
Abstract: Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for an apparatus comprising a thread dispatcher to dispatch a thread for execution; a compute unit having a single instruction, multiple thread architecture, the compute unit to execute multiple concurrent threads; and a memory coupled with the compute unit, the memory to store thread state for a suspended thread, wherein the compute unit is to: detect that all threads on the compute unit are blocked from execution, select a victim thread from the multiple concurrent threads, suspend the victim thread, store thread state of the victim thread to the memory, and replace the victim thread with an additional thread to be executed.
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公开(公告)号：US20180285157A1
公开(公告)日：2018-10-04
申请号：US15477025
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , David J. Cowperthwaite , Abhishek R. Appu , Joydeep Ray , Vasanth Ranganathan , Altug Koker , Balaji Vembu
Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.
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公开(公告)号：US20220405876A1
公开(公告)日：2022-12-22
申请号：US17738254
申请日：2022-05-06
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Balaji Vembu , Altug Koker , Bryan R. White , David J. Cowperthwaite , Joydeep Ray , Murali Ramadoss
Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.
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