公开(公告)号：US20220365709A1

公开(公告)日：2022-11-17

申请号：US17814724

申请日：2022-07-25

Applicant: Intel Corporation

Inventor： Arun Raghunath ,  Scott Peterson ,  Kimberly A. Malone

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that identifies a first namespace descriptor, a device memory descriptor, and a first request to execute a program on a logical volume that spans a plurality of physical drives, selects a first target drive from the plurality of physical drives based on the first namespace descriptor, and configures the first target drive to execute the program on first input data associated with the first namespace descriptor and write a first output of the program to a first memory region in an internal memory of the first target drive. In one example, the technology maps the device memory descriptor to the first memory region.

公开(公告)号：US20240241775A1

公开(公告)日：2024-07-18

申请号：US18618844

申请日：2024-03-27

Applicant: Intel Corporation

Inventor： Joseph Jacob Grecco ,  Kianoosh Zandifar ,  Kimberly Malone ,  Scott Peterson

IPC: G06F9/54

CPC classification number: G06F9/544

Abstract: Disclosed examples implement inter-process communication using a shared memory with a shared heap. Disclosed examples send a request from a first process to a second process, the request to cause allocation of a shared heap in shared memory; determine a first virtual address range of the first process for the shared heap in the shared memory based on the first virtual address range matching a second virtual address range from the second process in the shared memory; and write information from the first process to the shared heap, the information to be accessed by the second process from the shared heap.

公开(公告)号：US20240354107A1

公开(公告)日：2024-10-24

申请号：US18754447

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Frank Hady ,  Christopher J. Hughes ,  Scott Peterson

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30047 ,  G06F9/321 ,  G06F9/3836

Abstract: In one example, a processor includes: at least one core to execute instructions; and at least one cache memory coupled to the at least one core, the at least one cache memory to store data, at least some of the data a copy of data stored in a memory. The at least one core is to determine whether to conditionally offload a sequence of instructions for execution on a compute circuit associated with the memory, based at least in part on whether one or more first data is present in the at least one cache memory, the one or more first data for use during execution of the sequence of instructions. Other embodiments are described and claimed.

公开(公告)号：US20190042133A1

公开(公告)日：2019-02-07

申请号：US16023025

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Scott Peterson ,  Sujoy Sen

IPC: G06F3/06 ,  H04L29/08

Abstract: Technologies for providing adaptive data access request routing in a distributed storage system include a compute device. The compute device includes a redirector device to receive, from an initiator device, a request that identifies a data set to be accessed. The redirector device is also to determine, from a set of routing rules indicative of target devices associated with data sets, whether the identified data set is available in a storage server associated with the present redirector device, forward, in response to a determination that the identified data set is not available in a storage server associated with the present redirector device, the request to a target device associated with the data set in the routing rules, and send, to the initiator device, an identification of the target device associated with the data set in the routing rules. Other embodiments are also described and claimed.