公开(公告)号：US20240354107A1

公开(公告)日：2024-10-24

申请号：US18754447

申请日：2024-06-26

申请人： Intel Corporation

发明人： Frank Hady ,  Christopher J. Hughes ,  Scott Peterson

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30047 ,  G06F9/321 ,  G06F9/3836

摘要： In one example, a processor includes: at least one core to execute instructions; and at least one cache memory coupled to the at least one core, the at least one cache memory to store data, at least some of the data a copy of data stored in a memory. The at least one core is to determine whether to conditionally offload a sequence of instructions for execution on a compute circuit associated with the memory, based at least in part on whether one or more first data is present in the at least one cache memory, the one or more first data for use during execution of the sequence of instructions. Other embodiments are described and claimed.

公开(公告)号：US10318185B2

公开(公告)日：2019-06-11

申请号：US15200933

申请日：2016-07-01

申请人： Intel Corporation

发明人： Frank Hady

IPC分类号： G06F3/06 ,  G06F12/02

摘要： An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.

公开(公告)号：US20180004438A1

公开(公告)日：2018-01-04

申请号：US15200933

申请日：2016-07-01

申请人： Intel Corporation

发明人： Frank Hady

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0246 ,  G06F2212/7201 ,  Y02D10/13 ,  Y02D10/154

摘要： An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.