公开(公告)号：US20230369503A1

公开(公告)日：2023-11-16

申请号：US17742664

申请日：2022-05-12

申请人： Intel Corporation

发明人： Cheng Tan ,  Van H. Le ,  Akash Garg ,  Shokir A. Pardaev ,  Timothy Jen ,  Abhishek Anil Sharma ,  Thiruselvam Ponnusamy ,  Moira C. Vyner ,  Caleb Barrett ,  Forough Mahmoudabadi ,  Albert B. Chen ,  Travis W. Lajoie ,  Christopher M. Pelto

IPC分类号： H01L29/786 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417

CPC分类号： H01L29/78618 ,  H01L23/5226 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733

摘要： Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.