公开(公告)号：US20220359759A1

公开(公告)日：2022-11-10

申请号：US17308856

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Chieh-Jen Ku ,  Andre Baran ,  Bernhard Sell ,  David Goldstein ,  Timothy Jen

IPC: H01L29/786 ,  H01L29/51 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02

Abstract: Transistors with metal oxide channel material that is in-situ doped for desired charge carrier concentrations. The metal oxide channel material may be deposited by atomic layering of multiple constituent metals with an oxidation of each layer. Such an ALD process may be performed by cyclically depositing a precursor of one of the metals upon a substrate during a deposition phase, and oxidizing the absorbed precursor during an oxidation phase. For a quinary metal oxide, each of three metal precursors may be introduced and oxidized during the ALD process, and charge carrier concentrations may be modulated by further introducing a fourth metal precursor during the ALD process in a manner that disperses this dopant metal within the film at a significantly lower chemical concentration than the other metals.

公开(公告)号：US20230371233A1

公开(公告)日：2023-11-16

申请号：US17742628

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Forough Mahmoudabadi ,  Shailesh Kumar Madisetti ,  Van H. Le ,  Timothy Jen ,  Cheng Tan ,  Jisoo Kim ,  Miriam R. Reshotko ,  Vishak Venkatraman ,  Eva Vo ,  Yue Zhong ,  Yu-Che Chiu ,  Moshe Dolejsi ,  Lorenzo Ferrari ,  Akash Kannegulla ,  Deepyanti Taneja ,  Mark Armstrong ,  Kamal H. Baloch ,  Afrin Sultana ,  Albert B. Chen ,  Vamsi Evani ,  Yang Yang ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L27/10805 ,  H01L23/5283 ,  H01L29/78696 ,  H01L29/94

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

公开(公告)号：US20230369503A1

公开(公告)日：2023-11-16

申请号：US17742664

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Cheng Tan ,  Van H. Le ,  Akash Garg ,  Shokir A. Pardaev ,  Timothy Jen ,  Abhishek Anil Sharma ,  Thiruselvam Ponnusamy ,  Moira C. Vyner ,  Caleb Barrett ,  Forough Mahmoudabadi ,  Albert B. Chen ,  Travis W. Lajoie ,  Christopher M. Pelto

IPC: H01L29/786 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417

CPC classification number: H01L29/78618 ,  H01L23/5226 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733

Abstract: Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.

公开(公告)号：US20230369501A1

公开(公告)日：2023-11-16

申请号：US17742631

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Cheng Tan ,  Yu-Wen Huang ,  Hui-Min Chuang ,  Xiaojun Weng ,  Nikhil J. Mehta ,  Allen B. Gardiner ,  Shu Zhou ,  Timothy Jen ,  Abhishek Anil Sharma ,  Van H. Le ,  Travis W. Lajoie ,  Bernhard Sell

IPC: H01L29/786 ,  H01L27/108

CPC classification number: H01L29/78606 ,  H01L27/10814 ,  H01L29/78696 ,  H01L27/10873

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

公开(公告)号：US20230369508A1

公开(公告)日：2023-11-16

申请号：US17742644

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Timothy Jen ,  Prem Chanani ,  Cheng Tan ,  Brian Wadsworth ,  Andre Baran ,  James Pellegren ,  Christopher J. Wiegand ,  Van H. Le ,  Abhishek Anil Sharma ,  Shailesh Kumar Madisetti ,  Xiaojun Weng

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/78687 ,  H01L23/5283 ,  H01L29/7869 ,  H01L27/10814

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.

公开(公告)号：US20230369506A1

公开(公告)日：2023-11-16

申请号：US17742649

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Miriam R. Reshotko ,  Van H. Le ,  Travis W. Lajoie ,  Mark Armstrong ,  Cheng Tan ,  Timothy Jen ,  Moshe Dolejsi ,  Deepyanti Taneja

IPC: H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/78645 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10814

Abstract: Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.

公开(公告)号：US20230369444A1

公开(公告)日：2023-11-16

申请号：US17742656

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Albert B. Chen ,  Mark Armstrong ,  Afrin Sultana ,  Van H. Le ,  Travis W. Lajoie ,  Shailesh Kumar Madisetti ,  Timothy Jen ,  Cheng Tan ,  Moshe Dolejsi ,  Vishak Venkatraman ,  Christopher Ryder ,  Deepyanti Taneja

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L29/513 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733 ,  H01L23/5226

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

公开(公告)号：US20230369340A1

公开(公告)日：2023-11-16

申请号：US17742651

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Van H. Le ,  Timothy Jen ,  Vishak Venkatraman ,  Shailesh Kumar Madisetti ,  Cheng Tan ,  Harish Ganapathy ,  James Pellegren ,  Kamal H. Baloch ,  Abhishek Anil Sharma

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L27/1225 ,  H01L29/7869 ,  H01L23/5283 ,  H01L27/1255 ,  H01L27/10805

Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

公开(公告)号：US11955482B2

公开(公告)日：2024-04-09

申请号：US16876495

申请日：2020-05-18

Applicant: Intel Corporation

Inventor： Robert Ehlert ,  Timothy Jen ,  Alexander Badmaev ,  Shridhar Hegde ,  Sandrine Charue-Bakker

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having high phosphorous dopant concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon and phosphorous, the phosphorous having an atomic concentration in a core region of the silicon greater than an atomic concentration in a peripheral region of the silicon.

公开(公告)号：US20230369509A1

公开(公告)日：2023-11-16

申请号：US17742638

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Jisoo Kim ,  Xiaoye Qin ,  Timothy Jen ,  Harish Ganapathy ,  Van H. Le ,  Huiying Liu ,  Prem Chanani ,  Cheng Tan ,  Shailesh Kumar Madisetti ,  Abhishek Anil Sharma ,  Brian Wadsworth ,  Vishak Venkatraman ,  Andre Baran

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/7869 ,  H01L23/5283 ,  H01L27/10814

Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.