公开(公告)号：US20240097693A1

公开(公告)日：2024-03-21

申请号：US17933512

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Somnath KUNDU ,  Amy L. WHITCOMBE ,  Stefano PELLERANO ,  Peter SAGAZIO ,  Brent CARLTON

IPC: H03M1/10 ,  H04B1/40

CPC classification number: H03M1/1014 ,  H04B1/40

Abstract: An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.