公开(公告)号：US20250004781A1

公开(公告)日：2025-01-02

申请号：US18217295

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Zeshan CHISHTI ,  Gilles POKAM ,  Julien SEBOT ,  Ahmed YOUSSEF ,  Henry WONG ,  Michael UPTON ,  Srikanth SRINIVASAN

IPC: G06F9/38

Abstract: Methods and apparatus to implement adaptive branch prediction throttling are disclosed. In one embodiment, the method comprises determining, based on looking up a branch confidence data structure, whether a current branch in execution of a single thread is a low confidence branch in which a branch predictor of a processor has a low level of certainty that outcome of the current branch is predicted correctly; and comparing a branch misprediction rate, a microinstruction waste rate, and a cache missing rate of the single thread with their corresponding thresholds. The method further comprises throttling branch prediction of the current branch based on the determination of the current branch being a low confidence branch and one or more thresholds for the branch misprediction rate, the microinstructions waste rate, and the cache missing rate of the single thread being crossed.

公开(公告)号：US20200311019A1

公开(公告)日：2020-10-01

申请号：US16737779

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Srikanth SRINIVASAN ,  Chetan CHAUHAN ,  Rajesh SUNDARAM ,  Jawad B. KHAN

IPC: G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06N3/00

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.