公开(公告)号：US20210407564A1

公开(公告)日：2021-12-30

申请号：US17468210

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Chetan CHAUHAN ,  Jawad B. KHAN ,  Sandeep K. GULIANI ,  William K. WALLER

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/14

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

公开(公告)号：US20200311019A1

公开(公告)日：2020-10-01

申请号：US16737779

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Srikanth SRINIVASAN ,  Chetan CHAUHAN ,  Rajesh SUNDARAM ,  Jawad B. KHAN

IPC: G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06N3/00

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

公开(公告)号：US20220057961A1

公开(公告)日：2022-02-24

申请号：US17519799

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Chetan CHAUHAN ,  Sourabh DONGAONKAR ,  Jawad B. KHAN

IPC: G06F3/06

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored physical one-bit wide columns with each bit of the multi-bit wide logical column stored in a one-bit physical column in a different physical die. The multi-bit column is read by reading a one-bit physical column in each of the different physical die in parallel. The multi-bit wide logical column is arranged diagonally across M physical rows and M one-bit physical columns with each bit of the multi-bit wide logical column in the logical row stored in a different physical row and physical one-bit wide column in one of plurality of dies.

公开(公告)号：US20210224267A1

公开(公告)日：2021-07-22

申请号：US17227045

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Jawad B. KHAN ,  Chetan CHAUHAN ,  Dipanjan SENGUPTA ,  Mariano TEPPER ,  Theodore WILLKE ,  Richard L. COULSON

IPC: G06F16/2458 ,  G06F16/248 ,  G06F16/21 ,  G06F16/22 ,  G06N7/00

Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.

公开(公告)号：US20240078051A1

公开(公告)日：2024-03-07

申请号：US18389525

申请日：2023-11-14

Applicant: Intel Corporation

Inventor： Nilesh N. SHAH ,  Chetan CHAUHAN ,  Shigeki TOMISHIMA ,  Nahid HASSAN ,  Andrew Chaang LING

IPC: G06F3/06 ,  G06N5/04 ,  G11C13/00

CPC classification number: G06F3/0679 ,  G06F3/0613 ,  G06F3/0644 ,  G06N5/04 ,  G11C13/0004 ,  G11C13/0007

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

公开(公告)号：US20220284948A1

公开(公告)日：2022-09-08

申请号：US17824808

申请日：2022-05-25

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Chetan CHAUHAN ,  Jawad B. KHAN ,  Rajesh SUNDARAM ,  Sandeep K. GULIANI

IPC: G11C11/4097 ,  G11C11/406

Abstract: Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.

公开(公告)号：US20220179594A1

公开(公告)日：2022-06-09

申请号：US17681512

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Nilesh N. SHAH ,  Chetan CHAUHAN ,  Shigeki TOMISHIMA ,  Nahid HASSAN ,  Andrew Chaang LING

IPC: G06F3/06 ,  G11C13/00 ,  G06N5/04

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

公开(公告)号：US20210318805A1

公开(公告)日：2021-10-14

申请号：US17358222

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Jawad B. KHAN ,  Chetan CHAUHAN ,  Dipanjan SENGUPTA ,  Mariano TEPPER ,  Theodore WILLKE

IPC: G06F3/06 ,  G06K9/62

Abstract: Binary sparse encoding of data can be used to reduce an amount of data read from the stochastic associative memory while processing a query. Read performance of the stochastic associated memory is optimized to enhance the query throughput by modifying access patterns to reduce the time to read the stochastic associated memory. Read performance of the stochastic associative memory can be further improved through the use of cluster aware sharding and replication for parallelized similarity search. Clusters are partitioned across multiple Dual In-line Memory Modules (DIMMs), each DIMM including stochastic associative memory, to achieve maximum latency advantage.

公开(公告)号：US20200167098A1

公开(公告)日：2020-05-28

申请号：US16779086

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Nilesh N. SHAH ,  Chetan CHAUHAN ,  Shigeki TOMISHIMA ,  Nahid HASSAN ,  Andrew Chaang LING

IPC: G06F3/06 ,  G11C13/00 ,  G06N5/04

Abstract: Examples herein relate to a solid state drive that includes a media, a processing system, and a media command arbiter configured to permit execution of a specific allocation of storage and compute commands based on a configuration, wherein the media command arbiter is to transfer commands to the media based on the configuration. The media can be locally connected to a compute engine processing system that is configurable to perform computations on data stored in the media. The configuration can indicate a number of compute commands and storage commands that are permitted to be performed over a period of time or media bandwidth allocated to compute commands and storage commands. The processing system can include an inference engine that performs one or more of: data pattern recognition, image recognition, augmented reality overlay applications, face recognition, object recognition, or voice recognition, language translation.