公开(公告)号：US20220284948A1

公开(公告)日：2022-09-08

申请号：US17824808

申请日：2022-05-25

Applicant: Intel Corporation

Inventor： Sourabh DONGAONKAR ,  Chetan CHAUHAN ,  Jawad B. KHAN ,  Rajesh SUNDARAM ,  Sandeep K. GULIANI

IPC: G11C11/4097 ,  G11C11/406

Abstract: Column read enabled three dimensional cross-point memory is optimized to reduce delay time due to partition busy times incurred when reading from a same partition. A column read enabled memory media stores each entry of a logical column of an array of bits in contiguous different physical rows and different physical columns of the cross-point memory array than any other entry of the logical column. Subsets of the contiguous different physical rows are stored in different partitions to reduce the delay time incurred when performing column reads from a same partition to improve media management operation performance.

公开(公告)号：US20180253355A1

公开(公告)日：2018-09-06

申请号：US15909929

申请日：2018-03-01

Applicant: Intel Corporation

Inventor： Kiran PANGAL ,  Prashant S. DAMLE ,  Rajesh SUNDARAM ,  Shekoufeh QAWAMI ,  Julie M. WALKER ,  Doyle RIVERS

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/27 ,  H03M13/05 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

公开(公告)号：US20200311019A1

公开(公告)日：2020-10-01

申请号：US16737779

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Shigeki TOMISHIMA ,  Srikanth SRINIVASAN ,  Chetan CHAUHAN ,  Rajesh SUNDARAM ,  Jawad B. KHAN

IPC: G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06N3/00

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

公开(公告)号：US20190057737A1

公开(公告)日：2019-02-21

申请号：US16035443

申请日：2018-07-13

Applicant: Intel Corporation

Inventor： Shekoufeh QAWAMI ,  Rajesh SUNDARAM ,  David J. ZIMMERMAN ,  Blaise FANNING

IPC: G11C13/00 ,  G06F12/02 ,  G06F1/32 ,  G06F9/30 ,  G11C16/06

Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

公开(公告)号：US20170186471A1

公开(公告)日：2017-06-29

申请号：US14998185

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Shekoufeh QAWAMI ,  Michael J. ALLEN ,  Rajesh SUNDARAM

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C29/022 ,  G11C29/023 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2207/2254 ,  Y02D10/14

Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

公开(公告)号：US20200174705A1

公开(公告)日：2020-06-04

申请号：US16780632

申请日：2020-02-03

Applicant: Intel Corporation

Inventor： Shekoufeh QAWAMI ,  Philip HILLIER ,  Benjamin GRANIELLO ,  Rajesh SUNDARAM

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.