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公开(公告)号:US10528768B2
公开(公告)日:2020-01-07
申请号:US15706180
申请日:2017-09-15
Applicant: Intel Corporation
Inventor: Suchit Subhaschandra , Srivatsan Krishnan , Brent Thomas , Pratik Marolia
Abstract: Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.
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2.
公开(公告)号:US20190087606A1
公开(公告)日:2019-03-21
申请号:US15706180
申请日:2017-09-15
Applicant: Intel Corporation
Inventor: Suchit Subhaschandra , Srivatsan Krishnan , Brent Thomas , Pratik Marolia
Abstract: Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.
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