公开(公告)号：US20190005176A1

公开(公告)日：2019-01-03

申请号：US15640448

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Rameshkumar Illikkal ,  Ananth Sankaranarayanan ,  David Zimmerman ,  Pratik M. Marolia ,  Suchit Subhaschandra ,  Dave Minturn

IPC: G06F17/50 ,  G06F21/76 ,  G06F17/30 ,  G06F3/06 ,  G06F9/445

Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

公开(公告)号：US11238203B2

公开(公告)日：2022-02-01

申请号：US15640448

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Rameshkumar Illikkal ,  Ananth Sankaranarayanan ,  David Zimmerman ,  Pratik M. Marolia ,  Suchit Subhaschandra ,  Dave Minturn

IPC: G06F30/331 ,  G06F21/76 ,  G06F3/06 ,  G06F9/445 ,  G06F12/0817 ,  G06F21/79 ,  G06F30/34

Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.

公开(公告)号：US10528768B2

公开(公告)日：2020-01-07

申请号：US15706180

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Suchit Subhaschandra ,  Srivatsan Krishnan ,  Brent Thomas ,  Pratik Marolia

IPC: H04L29/06 ,  G06F21/76 ,  G06F21/31

Abstract: Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.

公开(公告)号：US20190087606A1

公开(公告)日：2019-03-21

申请号：US15706180

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Suchit Subhaschandra ,  Srivatsan Krishnan ,  Brent Thomas ,  Pratik Marolia

IPC: G06F21/76 ,  G06F21/31

CPC classification number: G06F21/76 ,  G06F21/31

Abstract: Methods and apparatus to provide user-level access authorization for cloud-based filed-programmable gate arrays are disclosed. An example apparatus includes a field-programmable gate array (FPGA) including a first memory and a second memory different from the first memory. The first memory stores a bitstream. The second memory stores a first user tag associated with the bitstream. The example apparatus further includes a kernel having an FPGA driver operatively coupled to the FPGA. The FPGA driver is to receive a command associated with accessing the FPGA from a user-executed application. The FPGA driver is further to identify a second user tag associated with the command. The FPGA driver is further to determine whether the command is to be accepted based on the second user tag.