公开(公告)号：US20190102229A1

公开(公告)日：2019-04-04

申请号：US15721858

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Monica Gupta ,  Russell J. Fenger ,  Vijay Dhanraj ,  Deepak Samuel Kirubakaran ,  Srividya Ambale ,  Israel Hirsh ,  Eliezer Weissmann ,  Hisham Abu-Salah

IPC: G06F9/50

Abstract: Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.