公开(公告)号：US10915356B2

公开(公告)日：2021-02-09

申请号：US16117091

申请日：2018-08-30

Applicant: Intel Corporation

Inventor： Ramakrishnan Sivakumar ,  Vijay Dhanraj ,  Russell Fenger ,  Guy Therien

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.

公开(公告)号：US11422849B2

公开(公告)日：2022-08-23

申请号：US16547767

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  Vijay Dhanraj ,  Russell Jerome Fenger ,  Hisham Abu-Salah ,  Eliezer Weissmann

IPC: G06F1/32 ,  G06F9/46 ,  G06F9/455 ,  G06F9/48 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F11/34

Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.

公开(公告)号：US20200272513A1

公开(公告)日：2020-08-27

申请号：US16740794

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunther ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US10545793B2

公开(公告)日：2020-01-28

申请号：US15720296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunther ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US20190042307A1

公开(公告)日：2019-02-07

申请号：US16117091

申请日：2018-08-30

Applicant: Intel Corporation

Inventor： Ramakrishnan Sivakumar ,  Vijay Dhanraj ,  Russell Fenger ,  Guy Therien

IPC: G06F9/48 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for technology that identifies a thread and selects a core from a plurality of processor cores in response to the selected core being available while satisfying a least used condition with respect to the plurality of processor cores. The technology may also schedule the thread to be executed on the selected core.

公开(公告)号：US11194381B2

公开(公告)日：2021-12-07

申请号：US16642203

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhinav Karhu ,  Russell Fenger ,  Vijay Dhanraj ,  Balaji Masanamuthu Chinnathurai

IPC: G06F1/3234 ,  G06F1/3228 ,  G06F11/30

Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.

公开(公告)号：US20210055958A1

公开(公告)日：2021-02-25

申请号：US16547767

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  Vijay Dhanraj ,  Russell Jerome Fenger ,  Hisham Abu-Salah ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F1/3296

Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.

公开(公告)号：US10372493B2

公开(公告)日：2019-08-06

申请号：US14978182

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Vijay Dhanraj ,  Gaurav Khanna ,  Russell J. Fenger ,  Monica Gupta

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50

Abstract: Apparatuses, methods and storage medium associated with scheduling of threads and/or virtual machines, are disclosed herein. In embodiments, an apparatus is provided with a scheduler of an operating system and/or a virtual machine monitor. The scheduler is to retrieve or receive capabilities of the cores of one or more multi-core processors of the apparatus with diverse capabilities, and schedule a plurality of threads for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and characteristics of the plurality of threads. The virtual machine monitor is to retrieve or receive capabilities of the cores, and schedule a plurality of virtual machines for execution on selected one or ones of the cores, based at least in part on the capabilities of the cores and respective priorities of the virtual machines. Other embodiments may be described and/or claimed.

公开(公告)号：US20190102221A1

公开(公告)日：2019-04-04

申请号：US15720296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US11593154B2

公开(公告)日：2023-02-28

申请号：US16228136

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Ahmad Samih ,  Rajshree Chabukswar ,  Russell Fenger ,  Shadi Khasawneh ,  Vijay Dhanraj ,  Muhammad Abozaed ,  Mukund Ramakrishna ,  Atsuo Kuwahara ,  Guruprasad Settuvalli ,  Eugene Gorbatov ,  Monica Gupta ,  Christine M. Lin

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F9/30

Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.