公开(公告)号：US20250004871A1

公开(公告)日：2025-01-02

申请号：US18217501

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Beeman STRONG ,  Stanislav BRATANOV ,  Markus METZGER ,  Jason W. BRANDT ,  Stalinselvaraj JEYASINGH

IPC: G06F11/07

Abstract: Apparatus and method for a processor trace trigger tracing. A processor, comprising: a plurality of processing cores configurable as a plurality of logical processors; processor trace circuitry to perform trace operations to capture and process information related to program code executed by one or more of the logical processors; a debug unit to perform debug operations and collect debug data related to execution of the program code; a performance monitoring unit (PMU) comprising a plurality of counter registers, the PMU to collect performance data related to execution of the program code; and a plurality of trigger units, each trigger unit associated with a logical processor of the plurality of logical processors and configured to communicate trigger event data to the processor trace circuitry in response to trigger events received from at least one of the debug unit and the PMU in accordance with values of configuration bits in a corresponding trigger unit configuration register.

公开(公告)号：US20190087586A1

公开(公告)日：2019-03-21

申请号：US16123593

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Francis X. McKEEN ,  Carlos V. ROZAS ,  Uday R. SAVAGAONKAR ,  Simon P. JOHNSON ,  Vincent SCARLATA ,  Michael A. GOLDSMITH ,  Ernie BRICKELL ,  Jiang Tao LI ,  Howard C. HERBERT ,  Prashant DEWAN ,  Stephen J. TOLOPKA ,  Gilbert NEIGER ,  David DURHAM ,  Gary GRAUNKE ,  Bernard LINT ,  Don A. VAN DYKE ,  Joseph CIHULA ,  Stalinselvaraj JEYASINGH ,  Stephen R. VAN DOREN ,  Dion RODGERS ,  John GARNEY ,  Asher ALTMAN

IPC: G06F21/60 ,  G06F21/53 ,  G06F21/72

Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.