公开(公告)号：US20230091974A1

公开(公告)日：2023-03-23

申请号：US17482897

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Ritu GUPTA ,  Stephen R. VAN DOREN

IPC: G06F12/06 ,  G06F12/0842

Abstract: Examples include techniques associated with mapping system memory physical addresses to proximity domains. Examples include mapping system memory physical addresses for a memory coupled with a multi-die system to proximity domains that include cores of a multi-core processor and the associated level 3 (L3) cache for use by each core included in a respective proximity domain. The mapping is to facilitate cache line ownership of a cache line in an L3 cache by an input/output device or agent located on a separate die from the multi-core processor.

公开(公告)号：US20190087586A1

公开(公告)日：2019-03-21

申请号：US16123593

申请日：2018-09-06

Applicant: Intel Corporation

Inventor： Francis X. McKEEN ,  Carlos V. ROZAS ,  Uday R. SAVAGAONKAR ,  Simon P. JOHNSON ,  Vincent SCARLATA ,  Michael A. GOLDSMITH ,  Ernie BRICKELL ,  Jiang Tao LI ,  Howard C. HERBERT ,  Prashant DEWAN ,  Stephen J. TOLOPKA ,  Gilbert NEIGER ,  David DURHAM ,  Gary GRAUNKE ,  Bernard LINT ,  Don A. VAN DYKE ,  Joseph CIHULA ,  Stalinselvaraj JEYASINGH ,  Stephen R. VAN DOREN ,  Dion RODGERS ,  John GARNEY ,  Asher ALTMAN

IPC: G06F21/60 ,  G06F21/53 ,  G06F21/72

Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

公开(公告)号：US20250123881A1

公开(公告)日：2025-04-17

申请号：US18927065

申请日：2024-10-25

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffry J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20230418655A1

公开(公告)日：2023-12-28

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/383 ,  G06F9/3004 ,  G06F9/30036

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220164218A1

公开(公告)日：2022-05-26

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.