公开(公告)号：US20180013676A1

公开(公告)日：2018-01-11

申请号：US15711027

申请日：2017-09-21

Applicant: Intel Corporation

Inventor： Steen K. Larsen ,  Bryan E. Veal ,  Daniel S. Lake ,  Travis T. Schluessler ,  Mazhar I. Memon

IPC: H04L12/801 ,  G06F1/32 ,  H04L12/12 ,  H04L12/861

Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

公开(公告)号：US20150163143A1

公开(公告)日：2015-06-11

申请号：US14628834

申请日：2015-02-23

Applicant: Intel Corporation

Inventor： Steen K. Larsen ,  Bryan E. Veal ,  Daniel S. Lake ,  Travis T. Schluessler ,  Mazhar I. Memon

IPC: H04L12/801 ,  G06F1/32

CPC classification number: H04L47/12 ,  G06F1/3209 ,  H04L12/12 ,  H04L49/90 ,  Y02B70/32 ,  Y02D50/40

Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括识别多核处理器的核心，对于分组缓冲器中接收的输入分组将被引导至多核处理器，并且如果核心断电，则发送第一消息以使得核心被供电 在进入分组到达分组缓冲器的头部之前。 描述和要求保护其他实施例。

公开(公告)号：US10819638B2

公开(公告)日：2020-10-27

申请号：US15711027

申请日：2017-09-21

Applicant: Intel Corporation

Inventor： Steen K. Larsen ,  Bryan E. Veal ,  Daniel S. Lake ,  Travis T. Schluessler ,  Mazhar I. Memon

IPC: H04L12/801 ,  G06F1/3209 ,  H04L12/12 ,  H04L12/861

Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

公开(公告)号：US09876720B2

公开(公告)日：2018-01-23

申请号：US14628834

申请日：2015-02-23

Applicant: Intel Corporation

Inventor： Steen K. Larsen ,  Bryan E. Veal ,  Daniel S. Lake ,  Travis T. Schluessler ,  Mazhar I. Memon

IPC: G06F1/32 ,  H04L12/801 ,  H04L12/12 ,  H04L12/861

CPC classification number: H04L47/12 ,  G06F1/3209 ,  H04L12/12 ,  H04L49/90 ,  Y02B70/32 ,  Y02D50/40

Abstract: In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.