公开(公告)号：US20190102227A1

公开(公告)日：2019-04-04

申请号：US15720222

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash Ananthakrishnan ,  Vijay Dhanraj ,  Russell Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth Sistla ,  Guy Therien ,  Ankush Verma ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.