公开(公告)号：US20220197822A1

公开(公告)日：2022-06-23

申请号：US17133570

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Gilbert NEIGER ,  Stephen ROBINSON ,  Dan BAUM ,  Ron GABOR

IPC: G06F12/1027 ,  G06F11/07

Abstract: Techniques to allow use of metadata in unused bits of virtual addresses are described. A processor of an aspect includes a decode circuit to decode a memory access instruction. The instruction to indicate one or more memory address operands that are to have address generation information and metadata. An execution circuit coupled with the decode circuit to generate a 64-bit virtual address based on the one or more memory address operands. The 64-bit virtual address having a bit 63, an X-bit address field starting at a bit 0 to store an address generated from the address generation information, and one or more metadata bits to store the metadata. The execution circuit also to perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20220309005A1

公开(公告)日：2022-09-29

申请号：US17214851

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Krishnakumar GANAPATHY ,  Venkateswara MADDURI ,  James ALLEN ,  James COLEMAN ,  Stephen ROBINSON

IPC: G06F12/0897 ,  G06F3/06

Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.