公开(公告)号：US20240370312A1

公开(公告)日：2024-11-07

申请号：US18775652

申请日：2024-07-17

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Jeff A. HUXEL ,  Jeffrey G. WIEDEMEIER ,  James D. ALLEN ,  Arvind RAMAN ,  Krishnakumar GANAPATHY

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  G06F11/07 ,  G06F11/16

Abstract: A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.

公开(公告)号：US20220309005A1

公开(公告)日：2022-09-29

申请号：US17214851

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Krishnakumar GANAPATHY ,  Venkateswara MADDURI ,  James ALLEN ,  James COLEMAN ,  Stephen ROBINSON

IPC: G06F12/0897 ,  G06F3/06

Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.

公开(公告)号：US20220206875A1

公开(公告)日：2022-06-30

申请号：US17134065

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Vedvyas SHANBHOGUE ,  Jeff A. HUXEL ,  Jeffrey G. WIEDEMEIER ,  James D. ALLEN ,  Arvind RAMAN ,  Krishnakumar GANAPATHY

IPC: G06F9/52 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

Abstract: A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.