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    DEVICE, SYSTEM, AND METHOD TO CONCURRENTLY STORE MULTIPLE PMON COUNTS IN A SINGLE REGISTER
    1.
    发明申请
    DEVICE, SYSTEM, AND METHOD TO CONCURRENTLY STORE MULTIPLE PMON COUNTS IN A SINGLE REGISTER 有权

    公开(公告)号：US20220196733A1

    公开(公告)日：2022-06-23

    申请号：US17131477

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Gaurav Porwal ,  Subhankar Panda ,  Theodros Yigzaw ,  John Holm

    IPC: G01R31/317

    Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

    Disambiguation of error logging during system reset
    3.
    发明授权
    Disambiguation of error logging during system reset 有权

    公开(公告)号：US10824493B2

    公开(公告)日：2020-11-03

    申请号：US15606799

    申请日：2017-05-26

    Applicant: Intel Corporation

    Inventor： Subhankar Panda ,  Gaurav Porwal

    IPC: G06F11/00 ,  G06F11/07

    Abstract: A mechanism for disambiguation of error logging during a warm reset is disclosed. A system agent detects an error occurring during bootstrapping of a processor package. The error occurs prior to initiation of a machine check system. A wide pulse event is initiated to signal a wide pulse register to store a wide pulse time stamp counter value. The wide pulse event also signals a lap register to store a lap time stamp counter value. The wide pulse register maintains the wide pulse time stamp counter value during a warm reset, and the lap register clears the lap time stamp counter value during the warm reset. The system agent obtains the wide pulse time stamp counter value and the lap time stamp counter value after bootstrapping is complete to determine an order of occurrence of the error relative to the warm reset.

    DELAYED ERROR PROCESSING
    4.
    发明申请
    DELAYED ERROR PROCESSING 审中-公开

    公开(公告)号：US20180349231A1

    公开(公告)日：2018-12-06

    申请号：US15610067

    申请日：2017-05-31

    Applicant: Intel Corporation

    Inventor： Subhankar Panda ,  Sarathy Jayakumar ,  Gaurav Porwal ,  Theodros Yigzaw

    IPC: G06F11/14

    CPC classification number: G06F11/0793 ,  G06F11/0772 ,  G06F11/0796 ,  G06F11/1415 ,  G06F11/142 ,  G06F11/1441

    Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

    Serializing machine check exceptions for predictive failure analysis
    5.
    发明授权
    Serializing machine check exceptions for predictive failure analysis 有权

    公开(公告)号：US11687391B2

    公开(公告)日：2023-06-27

    申请号：US17516584

    申请日：2021-11-01

    Applicant: Intel Corporation

    Inventor： Gaurav Porwal ,  Subhankar Panda ,  John G. Holm

    IPC: G06F11/07

    CPC classification number: G06F11/0724 ,  G06F11/079 ,  G06F11/0736 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/0793

    Abstract: Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.

    REMOTE DEBUG FOR SCALED COMPUTING ENVIRONMENTS
    7.
    发明申请
    REMOTE DEBUG FOR SCALED COMPUTING ENVIRONMENTS 审中-公开

    公开(公告)号：US20190004887A1

    公开(公告)日：2019-01-03

    申请号：US15640487

    申请日：2017-07-01

    Applicant: INTEL CORPORATION

    Inventor： Stalinselvaraj Jeyasingh ,  Subhankar Panda ,  David A. Locklear ,  Steven A. Filary ,  Christopher J. Stedman ,  Carlos Vallin

    IPC: G06F11/07 ,  G06F11/14

    Abstract: Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.

    Device, system, and method to concurrently store multiple PMON counts in a single register
    8.
    发明授权
    Device, system, and method to concurrently store multiple PMON counts in a single register 有权

    公开(公告)号：US12044730B2

    公开(公告)日：2024-07-23

    申请号：US17131477

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Gaurav Porwal ,  Subhankar Panda ,  Theodros Yigzaw ,  John Holm

    IPC: G01R31/28 ,  G01R31/317

    CPC classification number: G01R31/317

    Abstract: Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

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