公开(公告)号：US20240104022A1

公开(公告)日：2024-03-28

申请号：US17954232

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Aneesh Aggarwal ,  Georgii Tkachuk ,  Subhiksha Ravisundar ,  Youngsoo Choi ,  Niall McDonnell

IPC: G06F12/0897 ,  G06F12/06

CPC classification number: G06F12/0897 ,  G06F12/063

Abstract: An example of an apparatus may include a first cache organized as two or more portions, a second cache, and circuitry coupled to the first cache and the second cache to determine a designated portion allocation for data transferred from the first cache to the second cache, and track the designated portion allocation for the data transferred from the first cache to the second cache. Other examples are disclosed and claimed.

公开(公告)号：US20240168890A1

公开(公告)日：2024-05-23

申请号：US18058401

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Chitra Natarajan ,  Aneesh Aggarwal ,  Ritu Gupta ,  Niall Declan McDonnell ,  Kapil Sood ,  Youngsoo Choi ,  Asad Khan ,  Lokpraveen Mosur ,  Subhiksha Ravisundar ,  George Leonard Tkachuk

IPC: G06F12/12

CPC classification number: G06F12/12 ,  G06F2212/1021

Abstract: A processor package comprises a caching agent that is operable to respond to a first sequence of direct-to-cache (DTC) write misses to a partition in a set in a cache by writing data from those write misses to the partition. When the partition comprises W ways, the caching agent is operable to write data from those write misses to all W ways in the partition. After writing data from those write misses to the partition, and before any data from the partition in the set has been read, the caching agent is operable to receive a second sequence of DTC write misses to the partition, and in response, complete those write misses while retaining the data from the first sequence in at least W-1 of the ways in the partition. Other embodiments are described and claimed.