公开(公告)号：US20200152650A1

公开(公告)日：2020-05-14

申请号：US16184641

申请日：2018-11-08

Applicant: Intel Corporation

Inventor： Deepak Thimmegowda ,  Owen Jungroth ,  Khaled Hasnat ,  David Meyaard ,  Surendranath C. Eruvuru

IPC: H01L27/11556 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11519

Abstract: Embodiments of the present disclosure are directed towards a memory device with a split staircase, in accordance with some embodiments. In one embodiment, the memory device includes one or more pillars disposed in a die, and a plurality of wordlines formed in a stack of multiple tiers and coupled with the one or more pillars. At least some of the wordlines are split across the tiers into at least first and second portions. Respective ends of at least some wordlines of at least one of the first or second portions, at a location of the split, are exposed to provide electrical coupling with other components of the device. Other embodiments may be described and/or claimed.