公开(公告)号：US20220107897A1

公开(公告)日：2022-04-07

申请号：US17552239

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： David KEPPEL ,  Swapna RAJ ,  Kermin CHOFLEMING ,  Samantika S. SURY

IPC: G06F12/0842

Abstract: Examples described herein relate to circuitry to selectively disable cache snoop operations issued by a particular processor or its cache manager based on data in a memory address range, to be accessed by the particular processor, having been flushed from one or more other cache devices accessible to other processors. At or after completion of flushing or scrubbing data in the memory address range to memory, the particular processor or its cache manager do not issue snoop operations for accesses to the memory address range. In response to an access by some other device to the memory address range, the processor or cache manager may resume issuing snoop operations.

公开(公告)号：US20210224213A1

公开(公告)日：2021-07-22

申请号：US17206961

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Swapna RAJ ,  Samantika S. SURY ,  Kermin CHOFLEMING ,  Simon C. STEELY, JR.

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/0815

Abstract: Examples include techniques for near data acceleration for a multi-core architecture. A near data processor included in a memory controller of a processor may access data maintained in a memory device coupled with the near data processor via one or more memory channels responsive to a work request to execute a kernel, an application or a loop routine using the accessed data to generate values. The near data processor provides an indication to the requestor of the work request that values have been generated.