-
公开(公告)号：US12155474B2
公开(公告)日：2024-11-26
申请号：US17086085
申请日：2020-10-30
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Per E. Fornberg , Tal Israeli , Zuoguo Wu
Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.
-
公开(公告)号：US20210050941A1
公开(公告)日：2021-02-18
申请号：US17086085
申请日：2020-10-30
Applicant: Intel Corporation
Inventor： Debendra Das Sharma , Per E. Fornberg , Tal Israeli , Zuoguo Wu
Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.
-
Search Results
2
records
(took 0.018 seconds)
