公开(公告)号：US11934261B2

公开(公告)日：2024-03-19

申请号：US17580408

申请日：2022-01-20

申请人： Intel Corporation

发明人： Debendra Das Sharma

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/14 ,  G06F13/42 ,  H04L1/00 ,  H04L1/1812

CPC分类号： G06F11/1004 ,  G06F11/076 ,  G06F11/1402 ,  G06F13/4221 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/0083 ,  H04L1/009 ,  H04L1/1812

摘要： A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.

公开(公告)号：US20240012772A1

公开(公告)日：2024-01-11

申请号：US18347236

申请日：2023-07-05

申请人： Intel Corporation

发明人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC分类号： G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

CPC分类号： G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/4286 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30145 ,  G06F13/4221 ,  G06F12/0806 ,  G06F12/0833 ,  G06F9/466 ,  G06F13/4022 ,  G06F9/44505 ,  G06F13/4282 ,  G06F1/3287 ,  G06F13/4068 ,  G06F11/1004 ,  G06F13/4291 ,  H04L9/0662 ,  G06F12/0808 ,  H04L45/74

摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US11836101B2

公开(公告)日：2023-12-05

申请号：US16831719

申请日：2020-03-26

申请人： Intel Corporation

发明人： Debendra Das Sharma

IPC分类号： G06F13/362 ,  H04L69/324

CPC分类号： G06F13/362 ,  H04L69/324

摘要： A system can include a host device that includes a downstream port and an endpoint device that includes an upstream port. A bidirectional multilane link can interconnect the downstream port and the upstream port. The downstream port can send a request to the upstream port across the bidirectional multilane link to change a number of active lanes in a first direction on the bidirectional multilane link, the request comprising an indication of a desired link width, receive an acknowledgment from the upstream port to change the number of active lanes on the bidirectional multilane link to the desired link width in the first direction, configure the bidirectional multilane link to operate using the desired link width, and send or receiving data to the upstream port using the desired link width. The change in link width can be asymmetrical (i.e., the upstream link width is different from the downstream link width).

公开(公告)号：US11818058B2

公开(公告)日：2023-11-14

申请号：US17374545

申请日：2021-07-13

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H04L49/9005 ,  H04L12/40

CPC分类号： H04L49/9005 ,  H04L12/40

摘要： Systems, methods, and computer-readable media are disclosed for an apparatus coupled to a communication bus, where the apparatus includes a queue and a controller to manage operations of the queue. The queue includes a first space to store a first information for a first traffic type, with a first flow class, and for a first virtual channel of communication between a first communicating entity and a second communicating entity. The queue further includes a second space to store a second information for a second traffic type, with a second flow class, and for a second virtual channel of communication between a third communicating entity and a fourth communicating entity. The first traffic type is different from the second traffic type, the first flow class is different from the second flow class, or the first virtual channel is different from the second virtual channel. Other embodiments may be described and/or claimed.

公开(公告)号：US11755486B2

公开(公告)日：2023-09-12

申请号：US17236692

申请日：2021-04-21

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC分类号： G06F12/00 ,  G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

CPC分类号： G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

摘要： A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

公开(公告)号：US11675003B2

公开(公告)日：2023-06-13

申请号：US16725954

申请日：2019-12-23

申请人： Intel Corporation

发明人： Daniel S. Froelich ,  Debendra Das Sharma

IPC分类号： G01R31/317 ,  G06F11/22 ,  H04B3/46 ,  G01R31/3177 ,  G01R31/28 ,  G01R31/327 ,  G06F11/00 ,  G06F11/07 ,  G06F11/36 ,  G06F13/16 ,  H01L21/66

CPC分类号： G01R31/31703 ,  G01R31/3177 ,  G01R31/31725 ,  G06F11/221 ,  H04B3/46 ,  G01R31/2851 ,  G01R31/3275 ,  G06F11/00 ,  G06F11/0751 ,  G06F11/2205 ,  G06F11/3688 ,  G06F13/1689 ,  H01L22/34 ,  H01L2225/06596

摘要： A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

公开(公告)号：US11599497B2

公开(公告)日：2023-03-07

申请号：US17008363

申请日：2020-08-31

申请人： Intel Corporation

发明人： Zuoguo Wu ,  Debendra Das Sharma ,  Mohiuddin M. Mazumder ,  Jong-Ru Guo ,  Anupriya Sriramulu ,  Narasimha Lanka ,  Timothy Wig ,  Jeff Morriss

IPC分类号： G06F15/173 ,  H01L23/522 ,  H03K19/17736 ,  G06F15/16 ,  H01L21/768 ,  G06F9/28

摘要： A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

公开(公告)号：US20220342840A1

公开(公告)日：2022-10-27

申请号：US17852865

申请日：2022-06-29

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

IPC分类号： G06F13/42

摘要： A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

公开(公告)号：US20220255559A1

公开(公告)日：2022-08-11

申请号：US17681364

申请日：2022-02-25

申请人： Intel Corporation

发明人： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC分类号： H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

摘要： An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US20220114128A1

公开(公告)日：2022-04-14

申请号：US17559002

申请日：2021-12-22

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC分类号： G06F13/40 ,  H04L69/16 ,  G06F1/3237 ,  G06F13/42

摘要： Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.