利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

217 条记录 (耗时 0.035 秒)

    DIE-TO-DIE INTERCONNECT
    2.
    发明申请
    DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220342840A1

    公开(公告)日：2022-10-27

    申请号：US17852865

    申请日：2022-06-29

    申请人： Intel Corporation

    发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

    IPC分类号： G06F13/42

    摘要： A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

    Connecting accelerator resources using a switch
    6.
    发明授权
    Connecting accelerator resources using a switch 有权

    公开(公告)号：US11249808B2

    公开(公告)日：2022-02-15

    申请号：US15682896

    申请日：2017-08-22

    申请人： Intel Corporation

    发明人： Anil Rao ,  Debendra Das Sharma

    IPC分类号： G06F9/50 ,  G06F9/4401 ,  G06F9/48 ,  H04L67/10

    摘要： The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.

    Width and frequency conversion with PHY layer devices in PCI-express
    7.
    发明授权
    Width and frequency conversion with PHY layer devices in PCI-express 有权

    公开(公告)号：US11239843B2

    公开(公告)日：2022-02-01

    申请号：US16826001

    申请日：2020-03-20

    申请人： Intel Corporation

    发明人： Debendra Das Sharma

    IPC分类号： G06F13/40 ,  H03K19/17724 ,  G06F13/38 ,  G06F3/01 ,  G06F1/3203

    摘要： A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second link width different from the first link width; and physical layer logic to receive from the first port a first data block arranged according to the first link width and frequency; create at least one second data block arranged according the second link width and frequency, the at least one second data block including data bytes from the first data block arranged sequentially in the at least one second data block; and transmit the at least one second data block to the second port.

    FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE
    9.
    发明申请
    FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE 有权

    公开(公告)号：US20220012203A1

    公开(公告)日：2022-01-13

    申请号：US17485337

    申请日：2021-09-25

    申请人： Intel Corporation

    发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

    IPC分类号： G06F13/40 ,  G06F13/42

    摘要： Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

    ORDERED SETS FOR HIGH-SPEED INTERCONNECTS
    10.
    发明申请
    ORDERED SETS FOR HIGH-SPEED INTERCONNECTS 有权

    公开(公告)号：US20210367900A1

    公开(公告)日：2021-11-25

    申请号：US17397710

    申请日：2021-08-09

    申请人： Intel Corporation

    发明人： Debendra Das Sharma

    IPC分类号： H04L12/801 ,  H04L12/12 ,  H04L1/20

    摘要： A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.