公开(公告)号：US20180267850A1

公开(公告)日：2018-09-20

申请号：US15761405

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

IPC: G06F11/08 ,  G06F11/22 ,  G06F13/14 ,  H04L1/00

CPC classification number: G06F11/08 ,  G06F11/1004 ,  G06F11/221 ,  G06F13/14 ,  H04L1/0061

Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

公开(公告)号：US20210050941A1

公开(公告)日：2021-02-18

申请号：US17086085

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Per E. Fornberg ,  Tal Israeli ,  Zuoguo Wu

IPC: H04L1/00 ,  H03M13/09

Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.

公开(公告)号：US20250158738A1

公开(公告)日：2025-05-15

申请号：US18920362

申请日：2024-10-18

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Per E. Fornberg ,  Tal Israeli ,  Zuoguo Wu

IPC: H04L1/00 ,  H03M13/09

Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.

公开(公告)号：US12155474B2

公开(公告)日：2024-11-26

申请号：US17086085

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Per E. Fornberg ,  Tal Israeli ,  Zuoguo Wu

IPC: H04L1/00 ,  H03M13/00 ,  H03M13/09

Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.

公开(公告)号：US11157350B2

公开(公告)日：2021-10-26

申请号：US15929946

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

IPC: G06F11/08 ,  G06F13/14 ,  G06F11/10 ,  G06F11/22 ,  H04L1/00

Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

公开(公告)号：US20220200780A1

公开(公告)日：2022-06-23

申请号：US17690339

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Per E. Fornberg ,  Anoop Karunan ,  Aruna Kumar L S ,  Sunil Kumar CR ,  Sleiman Bou-Sleiman

IPC: H04L7/00 ,  G06F13/42 ,  G06F1/26

Abstract: A system comprising transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link.

公开(公告)号：US10671476B2

公开(公告)日：2020-06-02

申请号：US15761405

申请日：2015-09-26

Applicant: Intel Corporation ,  Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

Inventor： Daniel S. Froelich ,  Debendra Das Sharma ,  Fulvio Spagna ,  Per E. Fornberg ,  David Edward Bradley

IPC: G06F11/08 ,  G06F13/14 ,  G06F11/10 ,  G06F11/22 ,  H04L1/00

Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.