公开(公告)号：US11991025B2

公开(公告)日：2024-05-21

申请号：US17110228

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Itamar Levin ,  Tali Warshavsky

IPC: H04L25/03 ,  G06F13/42

CPC classification number: H04L25/03019 ,  G06F13/4282 ,  H04L2025/03636

Abstract: Examples described herein include setting an equalizer tap setting and gain setting in a serializer/deserializer (SerDes). In some examples, determining an equalizer setting and gain setting occurs by causing a mean-square error cost scheme tracking to lock to an offset from a minimum of a cost of the mean-square error cost scheme without pausing error cost tracking. In some examples, the mean-square error cost scheme comprises a least mean square (LMS) scheme. In some examples, determining an equalizer setting comprises: applying increases or decreases to an equalizer setting, and an increase to an equalizer setting can be a different amount than an amount of decrease to an equalizer setting.

公开(公告)号：US12261724B2

公开(公告)日：2025-03-25

申请号：US17484205

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Itamar Levin ,  Tali Warshavsky

IPC: H04L25/03 ,  G06F13/42 ,  H03G3/30 ,  H04B1/16

Abstract: An Automatic Gain Control (AGC) SERDES circuit may be used to provide improved gain control for SERDES operation. This AGC SERDES circuit uses an initial gain convergence to determine and store an initial gain level. Once the initial gain convergence is complete, the AGC SERDES circuit uses a signal peak tracking to reduce or prevent saturation events. By setting the gain target based on tracked changes in the equalizer coefficients, the AGC SERDES circuit adapts the gain target to reduce or prevent saturation events and provide the improved communication throughput. A SERDES receiver circuit also provides improved performance using an improved convergence flow within its subcomponent blocks. The improved convergence flow also provides the ability to track environmental changes, voltage changes, and changes to input parameters, and can be performed while data is running on the link to provide continuously improved communication channel performance.

公开(公告)号：US20230099103A1

公开(公告)日：2023-03-30

申请号：US17484105

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Itamar Levin ,  Tali Warshavsky ,  Yekutiel Uliel

IPC: H04L25/03 ,  H04L27/01

Abstract: A CTLE-based SERDES receiver circuit using ISI metering provides an improved SERDES I/O performance. The CTLE SERDES receiver circuit may include an analog receiver frontend to generate an analog-to-digital converter (ADC) digital signal and a reduced ISI signal, a data path circuit to generate a sliced data stream and sliced cursor error stream, a digital signal processing (DSP) circuit to generate a converged data stream, a multi-tap intersymbol interference (ISI) assessment circuit to generate a weighted ISI sum, and an ISI minimization circuit to generate a continuous time linear equalizer (CTLE) adaptation control signal based on the weighted ISI sum.