公开(公告)号：US08806290B2

公开(公告)日：2014-08-12

申请号：US13948772

申请日：2013-07-23

Applicant: Intel Corporation

Inventor： Tao Zhang ,  Yuan Li ,  Jianbin Zhu

IPC: H03M13/00 ,  H03M13/27 ,  G06F11/10 ,  H03M13/39 ,  H03M13/29

CPC classification number: G06F11/10 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2739 ,  H03M13/2957 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6505 ,  H03M13/6525 ,  H03M13/6561

Abstract: According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

Abstract translation: 根据一些实施例，提供了配置用于高速分组接入（HSPA）和长期演进（LTE）的turbo解码器，包括：多个最大后验（MAP）引擎; 由多个MAP引擎的MAP引擎访问的多个外部存储器组; 并且其中当所述turbo解码器以HSDPA模式操作时，所述多个非本征存储体被配置为使得在解码迭代的前半部分期间，MAP引擎能够从第二数据集读取第一数据集并将第二数据集写入到所述多个外部 存储器组以自然行和列顺序排列，并且在解码迭代的后半段期间，MAP引擎能够以预定的行和列顺序从第二数据集读取和写入第四数据集到多个外部存储体 根据使用读列缓冲器和写列缓冲器的交织器表。