公开(公告)号：US20220196507A1

公开(公告)日：2022-06-23

申请号：US17133554

申请日：2020-12-23

申请人： Intel Corporation

发明人： Prabhakar SUBRAHMANYAM ,  Yi XIA ,  Ying-Feng PANG ,  Victor POLYANKO ,  Mark BIANCO ,  Bijoyraj SAHU ,  Minh T.D. LE ,  Carlos ALVIZO FLORES ,  Javier AVALOS GARCIA ,  Adriana LOPEZ INIGUEZ ,  Luz Karine SANDOVAL GRANADOS ,  Michael BERKTOLD ,  Damion SEARLS ,  Jin YANG ,  David SHIA ,  Samer MELHEM ,  Jeffrey Ryan CONNER ,  Hemant DESAI ,  John RAATZ ,  Richard DISCHLER ,  Bergen ANDERSON ,  Eric W. BUDDRIUS ,  Kenan ARIK ,  Barrett M. FANEUF ,  Lianchang DU ,  Yuehong FAN ,  Shengzhen ZHANG ,  Yuyang XIA ,  Jun ZHANG ,  Yuan Li ,  Catharina BIBER ,  Kristin L. WELDON ,  Brendan T. PAVELEK

IPC分类号： G01M3/04 ,  G01M3/16 ,  G01M3/20 ,  H05K7/20

摘要： An apparatus is described. The apparatus includes a cover to enclose a junction between respective ends of first and second fluidic conduits. The first and second fluidic conduits transport a coolant fluid within an electronic system. The apparatus also includes a leak detection device to be located within a region that is enclosed by the cover when the junction is enclosed by the cover. The leak detection device is to detect a leak of the coolant fluid at the junction when the junction is enclosed by the cover. The first and second fluidic conduits extend outside the cover when the junction is enclosed by the cover. Another apparatus is also described. The other apparatus includes a leak detection device to detect a leak of coolant fluid from a specific component or junction in a liquid cooling system of an electronic system.

公开(公告)号：US10084486B1

公开(公告)日：2018-09-25

申请号：US15720905

申请日：2017-09-29

申请人： Intel Corporation

发明人： Jianbin Zhu ,  Yi Zhou ,  Yuzhou Zhang ,  Yuan Li ,  Chuong Vu

IPC分类号： H04L5/12 ,  H04L23/02 ,  H03M13/29 ,  H04L1/00 ,  H03M13/39 ,  H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/3972 ,  H03M13/6561 ,  H03M13/658 ,  H04L1/0055

摘要： A method for decoding a received code using a device that includes: an antenna for receiving a signal over a wireless channel, and instances of a Maximum-A-Posteriori (MAP) turbo decoder for decoding a segment of the received code, are disclosed. For example, the method, by forward and backward gamma engines, for each window, concurrently computes gamma branch metrics in forward and backward directions, respectively, by forward and backward state metric engines comprising respective lambda engines and coupled to the respective gamma engines, for each window, sequentially computes forward and backward state metrics, respectively, based on respective gamma branch metrics and respective initial values, by the lambda engines, determines Log Likelihood Ratios (LLRs) and soft decisions, and by a post-processor, computes extrinsic data based on the forward and backward state metrics for any subsequent iteration as at least a portion of the a-priori information and otherwise provides a decoded segment.

公开(公告)号：US08806290B2

公开(公告)日：2014-08-12

申请号：US13948772

申请日：2013-07-23

申请人： Intel Corporation

发明人： Tao Zhang ,  Yuan Li ,  Jianbin Zhu

IPC分类号： H03M13/00 ,  H03M13/27 ,  G06F11/10 ,  H03M13/39 ,  H03M13/29

CPC分类号： G06F11/10 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2739 ,  H03M13/2957 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6505 ,  H03M13/6525 ,  H03M13/6561

摘要： According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

摘要翻译： 根据一些实施例，提供了配置用于高速分组接入（HSPA）和长期演进（LTE）的turbo解码器，包括：多个最大后验（MAP）引擎; 由多个MAP引擎的MAP引擎访问的多个外部存储器组; 并且其中当所述turbo解码器以HSDPA模式操作时，所述多个非本征存储体被配置为使得在解码迭代的前半部分期间，MAP引擎能够从第二数据集读取第一数据集并将第二数据集写入到所述多个外部 存储器组以自然行和列顺序排列，并且在解码迭代的后半段期间，MAP引擎能够以预定的行和列顺序从第二数据集读取和写入第四数据集到多个外部存储体 根据使用读列缓冲器和写列缓冲器的交织器表。