公开(公告)号：US20190096503A1

公开(公告)日：2019-03-28

申请号：US15717721

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Sreejit CHAKRAVARTY ,  Fei SU ,  Puneet GUPTA ,  Wei Ming LIM ,  Terrence Huat Hin TAN ,  Amit SANGHANI ,  Anubhav SINHA ,  Sudheer V BADANA ,  Rakesh KANDULA ,  Adithya B. S.

IPC: G11C29/12 ,  G11C29/48 ,  H01L23/538 ,  H01L25/065 ,  H03K17/00 ,  H03K17/56

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).