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公开(公告)号:US11886910B2
公开(公告)日:2024-01-30
申请号:US16728175
申请日:2019-12-27
Applicant: Intel Corporation
Inventor: Yanru Li , William Zand , Thomas Klingenbrunn , Ali Taha
IPC: G06F9/46 , G06F9/48 , G06F12/1009 , G06F13/16
CPC classification number: G06F9/4881 , G06F9/466 , G06F12/1009 , G06F13/1605 , G06F2213/0038
Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.
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公开(公告)号:US20210200579A1
公开(公告)日:2021-07-01
申请号:US16728175
申请日:2019-12-27
Applicant: Intel Corporation
Inventor: Yanru Li , William Zand , Thomas Klingenbrunn , Ali Taha
IPC: G06F9/48 , G06F9/46 , G06F13/16 , G06F12/1009
Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.
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