公开(公告)号：US20210116982A1

公开(公告)日：2021-04-22

申请号：US17133226

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rahul Khanna ,  Xin Kang ,  Ali Taha ,  James Tschanz ,  William Zand ,  Robert Kwasnick

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/3287 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

公开(公告)号：US12130688B2

公开(公告)日：2024-10-29

申请号：US17133226

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rahul Khanna ,  Xin Kang ,  Ali Taha ,  James Tschanz ,  William Zand ,  Robert Kwasnick

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

公开(公告)号：US11886910B2

公开(公告)日：2024-01-30

申请号：US16728175

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Yanru Li ,  William Zand ,  Thomas Klingenbrunn ,  Ali Taha

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/1009 ,  G06F13/16

CPC classification number: G06F9/4881 ,  G06F9/466 ,  G06F12/1009 ,  G06F13/1605 ,  G06F2213/0038

Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.

公开(公告)号：US20210200579A1

公开(公告)日：2021-07-01

申请号：US16728175

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Yanru Li ,  William Zand ,  Thomas Klingenbrunn ,  Ali Taha

IPC: G06F9/48 ,  G06F9/46 ,  G06F13/16 ,  G06F12/1009

Abstract: Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.