公开(公告)号：US20160164281A1

公开(公告)日：2016-06-09

申请号：US15043370

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Todd W. Mellinger ,  Michael E. Griffith ,  Ganesh Balamurugan ,  Thomas P. Thomas

IPC: H02H9/04 ,  G06F1/16 ,  H03K19/003 ,  H01L27/02

CPC classification number: H02H9/046 ,  G06F1/16 ,  G06F1/1613 ,  H01L27/0255 ,  H03K19/00361

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Abstract translation: 一个封装接口。 第一组第一组单端发射机电路。 第二组芯片上的第一组单端接收器电路。 接收器电路具有包括反相器和电阻反馈元件的终端电路。 多条导线耦合第一组发射机电路和第一组接收机电路。 多条导线的长度相匹配。

公开(公告)号：US10374419B2

公开(公告)日：2019-08-06

申请号：US15043370

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Todd W. Mellinger ,  Michael E. Griffith ,  Ganesh Balamurugan ,  Thomas P. Thomas

IPC: H02H9/04 ,  H01L27/02 ,  H03K19/003 ,  G06F1/16

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

公开(公告)号：US10122209B1

公开(公告)日：2018-11-06

申请号：US15628375

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Ahmed Fouad Salama ,  Srikrishnan Venkataraman ,  Todd W. Mellinger ,  Michael J. Hill ,  Paul K. Tucker ,  Assaf Benhamou

IPC: G05F1/00 ,  G05F1/565 ,  H02J13/00 ,  H02J3/06 ,  B06B1/02 ,  H02J5/00 ,  H02J50/80 ,  H04J14/02

Abstract: An apparatus system is provided which comprises: a first component to receive a first signal via a first delay circuit; a second component to receive a second signal via a second delay circuit; and one or more circuitries to tune a first delay of the first delay circuit and a second delay of the second delay circuit, based at least in part on monitoring of a voltage level.