公开(公告)号：US20210200685A1

公开(公告)日：2021-07-01

申请号：US16729371

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomar Stark

IPC: G06F12/0895 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/1045

Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.