公开(公告)号：US20210200685A1

公开(公告)日：2021-07-01

申请号：US16729371

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomar Stark

IPC: G06F12/0895 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/1045

Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

公开(公告)号：US11782716B2

公开(公告)日：2023-10-10

申请号：US17517580

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Michael LeMay ,  Vedvyas Shanbhogue ,  Deepak Gupta ,  Ravi Sahita ,  David M. Durham ,  Willem Pinckaers ,  Enrico Perla

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/448 ,  G06F9/46 ,  G06F16/901 ,  G06F9/455 ,  G06F12/14 ,  G06F21/52 ,  G06F21/79 ,  G06F9/35

CPC classification number: G06F9/30145 ,  G06F9/3836 ,  G06F9/449 ,  G06F9/468 ,  G06F16/9017

Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

公开(公告)号：US11693785B2

公开(公告)日：2023-07-04

申请号：US16728527

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomer Stark ,  Joseph Nuzman

IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/1081 ,  G06F12/1009 ,  G06F12/0811 ,  G06F12/14 ,  G06F9/30 ,  G06F11/30

CPC classification number: G06F12/0895 ,  G06F9/30043 ,  G06F9/30101 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/1466 ,  G06F2212/7207

Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

公开(公告)号：US11656998B2

公开(公告)日：2023-05-23

申请号：US16729371

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomer Stark

IPC: G06F12/00 ,  G06F12/0895 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/14

CPC classification number: G06F12/0895 ,  G06F12/1009 ,  G06F12/1054 ,  G06F12/1441 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

公开(公告)号：US11163569B2

公开(公告)日：2021-11-02

申请号：US16729358

申请日：2019-12-28

Applicant: Intel Corporation

Inventor： Michael Lemay ,  Vedvyas Shanbhogue ,  Deepak Gupta ,  Ravi Sahita ,  David M. Durham ,  Willem Pinckaers ,  Enrico Perla

IPC: G06F16/90 ,  G06F12/14 ,  G06F12/1009 ,  G06F9/30 ,  G06F9/38 ,  G06F16/901 ,  G06F9/46 ,  G06F9/448

Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.