公开(公告)号：US11385704B2

公开(公告)日：2022-07-12

申请号：US17183518

申请日：2021-02-24

申请人： Intel Corporation

发明人： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC分类号： G06F1/32 ,  G06F1/324 ,  G06F1/3206

摘要： In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US20210200685A1

公开(公告)日：2021-07-01

申请号：US16729371

申请日：2019-12-28

申请人： Intel Corporation

发明人： Ron Gabor ,  Enrico Perla ,  Raanan Sade ,  Igor Yanover ,  Tomar Stark

IPC分类号： G06F12/0895 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/1045

摘要： An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

公开(公告)号：US10891230B1

公开(公告)日：2021-01-12

申请号：US16458017

申请日：2019-06-29

申请人： Intel Corporation

发明人： Ron Gabor ,  Igor Yanover

IPC分类号： G06F9/34 ,  G06F12/0811

摘要： Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

公开(公告)号：US20200310511A1

公开(公告)日：2020-10-01

申请号：US16369793

申请日：2019-03-29

申请人： Intel Corporation

发明人： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC分类号： G06F1/324 ,  G06F1/3206

摘要： In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US10095522B2

公开(公告)日：2018-10-09

申请号：US14581268

申请日：2014-12-23

申请人： Intel Corporation

发明人： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/30

摘要： A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

公开(公告)号：US09710389B2

公开(公告)日：2017-07-18

申请号：US14643354

申请日：2015-03-10

申请人： INTEL CORPORATION

发明人： Oleg Margulis ,  Sumit Ahuja ,  Polychronis Xekalakis ,  Yongjun Park ,  Vineeth Mekkat ,  Igor Yanover ,  Sebastian Winkel ,  Ethan Schuchman

IPC分类号： G06F12/06 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F12/0875 ,  G06F9/38 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/467 ,  G06F2212/1008 ,  G06F2212/452

摘要： A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.

公开(公告)号：US09292362B2

公开(公告)日：2016-03-22

申请号：US13926089

申请日：2013-06-25

申请人： Intel Corporation

发明人： Lev Makovsky ,  Zeev Sperber ,  Efraim Rotem ,  Nir Rosenzweig ,  Stanislav Shwartsman ,  Raanan Sade ,  Igor Yanover ,  Gavri Berger ,  Tomer Weiner ,  Ron Gabor

IPC分类号： G06F1/04 ,  G06F9/54 ,  G06F9/30 ,  G06F9/48 ,  G06F1/32

CPC分类号： G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

摘要： In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US12106100B2

公开(公告)日：2024-10-01

申请号：US16487421

申请日：2017-07-01

申请人： Intel Corporation

发明人： Robert Valentine ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Bret L. Toll ,  Raanan Sade ,  Igor Yanover ,  Yuri Gebil ,  Rinat Rappoport ,  Stanislav Shwartsman ,  Menachem Adelman ,  Simon Rubanovich

IPC分类号： G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC分类号： G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

摘要： Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US12099597B2

公开(公告)日：2024-09-24

申请号：US18384996

申请日：2023-10-30

申请人： Intel Corporation

发明人： Alexander Gendler ,  Sagi Meller ,  Gavri Berger ,  Igor Yanover

IPC分类号： G06F21/00 ,  G06F1/32 ,  G06F9/38 ,  G06F21/54 ,  G06F21/56

CPC分类号： G06F21/54 ,  G06F1/32 ,  G06F9/3802 ,  G06F21/561 ,  G06F2221/034

摘要： An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

公开(公告)号：US11580031B2

公开(公告)日：2023-02-14

申请号：US16813346

申请日：2020-03-09

申请人： INTEL CORPORATION

发明人： Stanislav Shwartsman ,  Igor Yanover ,  Assaf Zaltsman ,  Ron Rais

IPC分类号： G06F12/1027 ,  G06F9/30

摘要： Systems, methods, and apparatuses relating to hardware for split data translation lookaside buffers. In one embodiment, a processor includes a decode circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, and a memory circuit comprising a load data translation lookaside buffer circuit and a store data translation lookaside buffer circuit separate and distinct from the load data translation lookaside buffer circuit, wherein the memory circuit sends a memory access request of the instructions to the load data translation lookaside buffer circuit when the memory access request is a load data request and to the store data translation lookaside buffer circuit when the memory access request is a store data request to determine a physical address for a virtual address of the memory access request.