公开(公告)号：US10540260B2

公开(公告)日：2020-01-21

申请号：US15903393

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  Elmoustapha Ould-Ahmed-Vall ,  John Gierach ,  Tomer Bar On ,  Devan Burke

IPC: G06F9/44 ,  G06F11/36 ,  G06F9/38 ,  G06T1/20

Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.

公开(公告)号：US20190266069A1

公开(公告)日：2019-08-29

申请号：US15903393

申请日：2018-02-23

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  Elmoustapha Ould-Ahmed-Vall ,  John Gierach ,  Tomer Bar On ,  Devan Burke

IPC: G06F11/36 ,  G06F9/38

Abstract: In one example, an apparatus comprises processing circuitry to analyze a program at compile time to determine a set of latency parameters associated with instruction sets implemented to execute the program and select a latency management technique based at least in part on the set of latency parameters associated with instruction sets implemented to execute the program. Other examples may be described and claimed.