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    Coarse compute shading
    1.
    发明授权
    Coarse compute shading 有权

    公开(公告)号：US10853989B2

    公开(公告)日：2020-12-01

    申请号：US16142692

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： John Gierach

    IPC: G06T15/00 ,  G06T15/80

    Abstract: Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.

    GPU based shader constant folding
    2.
    发明授权
    GPU based shader constant folding 有权

    公开(公告)号：US10748323B2

    公开(公告)日：2020-08-18

    申请号：US16208632

    申请日：2018-12-04

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Srividya Karumuri ,  Thomas Raoux ,  Devan Burke ,  Wojtek Rajski ,  Jeremy Brennan

    IPC: G06T15/50 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60

    Abstract: Embodiments described herein provide a general purpose graphics processing device, comprising a general purpose graphics processing compute block to process a workload including graphics or compute operations, a memory, and a constant folding unit comprising a processing unit to receive a first input shader and metadata for the first input shader, receive a first constant buffer comprising runtime constants for the first input shader, and generate an improved shader from the first input shader and the runtime constants. Other embodiments may be described and claimed.

    TILE-BASED MULTIPLE RESOLUTION RENDERING OF IMAGES
    3.
    发明申请
    TILE-BASED MULTIPLE RESOLUTION RENDERING OF IMAGES 审中-公开

    公开(公告)号：US20190355091A1

    公开(公告)日：2019-11-21

    申请号：US15982680

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

    IPC: G06T3/40 ,  G06T1/20

    Abstract: Embodiments are generally directed to tile-based multiple resolution rendering of images. An embodiment of an apparatus includes one or more processor cores; a plurality of tiling bins, the plurality of tiling bins including a bin for each of a plurality of tiles in an image; and a memory to store data for rendering of an image in one or more of a plurality of resolutions. The apparatus is to generate, in the memory, storage for a resolution setting for each the plurality of tiling bins and storage for a final render target, each tile of the final render target being rendered based on a respective tiling bin in the plurality of tiling bins.

    OUT-OF-ORDER PIXEL SHADING AND RASTERIZATION
    4.
    发明申请
    OUT-OF-ORDER PIXEL SHADING AND RASTERIZATION 有权

    公开(公告)号：US20220414967A1

    公开(公告)日：2022-12-29

    申请号：US17357403

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Prasoonkumar Surti ,  Jorge Garcia Pabon ,  John Gierach

    IPC: G06T15/00 ,  G06T1/20 ,  G06T15/10

    Abstract: Methods, systems and apparatuses may provide for technology that determines that a state of a plurality of primitives is associated with out-of-order execution. The plurality of primitives is associated with a raster order. The technology reorders the plurality of primitives from a raster order, and distributes one or more of pixel processing operations or rasterization operations associated with the plurality of primitives to load balance across one or more of a plurality of execution units of a graphics processor or a graphics pipeline of the graphics processor.

    GPU mixed primitive topology type processing
    5.
    发明授权
    GPU mixed primitive topology type processing 有权

    公开(公告)号：US10733690B2

    公开(公告)日：2020-08-04

    申请号：US15982693

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

    IPC: G06T1/20 ,  G06T17/10

    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING
    6.
    发明申请
    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING 审中-公开

    公开(公告)号：US20190355084A1

    公开(公告)日：2019-11-21

    申请号：US15982693

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

    IPC: G06T1/20 ,  G06T17/10

    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING
    8.
    发明申请
    GPU MIXED PRIMITIVE TOPOLOGY TYPE PROCESSING 有权

    公开(公告)号：US20210012452A1

    公开(公告)日：2021-01-14

    申请号：US16943984

    申请日：2020-07-30

    Applicant: Intel Corporation

    Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

    IPC: G06T1/20 ,  G06T17/10

    Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

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