公开(公告)号：US12125133B2

公开(公告)日：2024-10-22

申请号：US18371614

申请日：2023-09-22

申请人： Intel Corporation

发明人： Gabor Liktor ,  Karthik Vaidyanathan ,  Jefferson Amstutz ,  Atsuo Kuwahara ,  Michael Doyle ,  Travis Schluessler

IPC分类号： G06T15/00 ,  G06T1/60 ,  G06T15/06

CPC分类号： G06T15/005 ,  G06T1/60 ,  G06T15/06 ,  G06T2210/21

摘要： Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20210390058A1

公开(公告)日：2021-12-16

申请号：US16902909

申请日：2020-06-16

申请人： Intel Corporation

发明人： Sudarshanram Shetty ,  Ping Hang Cheung ,  Aravindh Anantaraman ,  Travis Schluessler

IPC分类号： G06F12/0893 ,  G06F12/0873 ,  G06F12/0862 ,  G06F9/30 ,  G06F9/50 ,  G06F11/30

摘要： An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.

公开(公告)号：US20210256653A1

公开(公告)日：2021-08-19

申请号：US17115555

申请日：2020-12-08

申请人： Intel Corporation

发明人： Saurabh Sharma ,  Michael Apodaca ,  Aditya Navale ,  Travis Schluessler ,  Vamsee Vardhan Chivukula ,  Abhishek Venkatesh ,  Subramaniam Maiyuran

IPC分类号： G06T1/20

摘要： An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

公开(公告)号：US10997686B2

公开(公告)日：2021-05-04

申请号：US16243624

申请日：2019-01-09

申请人： Intel Corporation

发明人： Balaji Vembu ,  Brandon Fliflet ,  James Valerio ,  Michael Apodaca ,  Ben Ashbaugh ,  Hema Nalluri ,  Ankur Shah ,  Murali Ramadoss ,  David Puffer ,  Altug Koker ,  Aditya Navale ,  Abhishek R. Appu ,  Joydeep Ray ,  Travis Schluessler

IPC分类号： G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/52 ,  G06T1/60

摘要： Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

公开(公告)号：US10861126B1

公开(公告)日：2020-12-08

申请号：US16449034

申请日：2019-06-21

申请人： Intel Corporation

发明人： Saurabh Sharma ,  Michael Apodaca ,  Aditya Navale ,  Travis Schluessler ,  Vamsee Vardhan Chivukula ,  Abhishek Venkatesh ,  Subramaniam Maiyuran

IPC分类号： G06T1/20

摘要： An apparatus to facilitate asynchronous execution at a processing unit. The apparatus includes one or more processors to detect independent task passes that may be executed out of order in a pipeline of the processing unit, schedule a first set of processing tasks to be executed at a first set of processing elements at the processing unit and schedule a second set of tasks to be executed at a second set of processing elements, wherein execution of the first set of tasks at the first set of processing elements is to be performed simultaneous and in parallel to execution of the second set of tasks at the second set of processing elements.

公开(公告)号：US10733690B2

公开(公告)日：2020-08-04

申请号：US15982693

申请日：2018-05-17

申请人： Intel Corporation

发明人： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC分类号： G06T1/20 ,  G06T17/10

摘要： Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US20190355084A1

公开(公告)日：2019-11-21

申请号：US15982693

申请日：2018-05-17

申请人： Intel Corporation

发明人： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC分类号： G06T1/20 ,  G06T17/10

摘要： Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US10445923B2

公开(公告)日：2019-10-15

申请号：US15719381

申请日：2017-09-28

申请人： Intel Corporation

发明人： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

IPC分类号： G06T15/04 ,  G06T15/00 ,  G06T15/80

摘要： One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.

公开(公告)号：US20190096117A1

公开(公告)日：2019-03-28

申请号：US15719381

申请日：2017-09-28

申请人： Intel Corporation

发明人： Devan Burke ,  Abhishek Venkatesh ,  Travis Schluessler

IPC分类号： G06T15/04 ,  G06T15/80 ,  G06T15/00

CPC分类号： G06T15/04 ,  G06T15/005 ,  G06T15/80

摘要： One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.

公开(公告)号：US11710269B2

公开(公告)日：2023-07-25

申请号：US17876358

申请日：2022-07-28

申请人： Intel Corporation

发明人： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC分类号： G06T15/00 ,  G06T15/40 ,  G06T15/80

CPC分类号： G06T15/005 ,  G06T15/40 ,  G06T15/80 ,  G06T2210/52

摘要： Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.