公开(公告)号：US20190340812A1

公开(公告)日：2019-11-07

申请号：US15972644

申请日：2018-05-07

Applicant: Intel Corporation

Inventor： VALENTIN FUETTERLING ,  GABOR LIKTOR ,  KARTHIK VAIDYANATHAN

IPC: G06T17/20 ,  G06T7/20 ,  G06T15/00 ,  G06T9/00 ,  G06T19/20

Abstract: A system and method for adaptive hierarchical tessellation. For example, one embodiment of a method comprises: a tessellation queue to store portions of a first image frame to be tessellated; motion vector analysis circuitry to group a plurality of sub-tiles within each of a plurality of tiles at multiple levels of granularity, wherein the sub-tiles of a first level comprise pixels and the sub-tiles of each successive level comprise tiles from a previous level, the motion vector analysis circuitry to iteratively analyze motion vectors of each group of sub-tiles at each level of granularity to determine whether the motion vectors are similar in accordance with a defined threshold, the motion vector analysis circuitry to queue tiles having sub-tiles which are determined to be dissimilar to the tessellation queue.